A convolution accelerator built around a 16 by 16 systolic PE array of 256 INT8 multiply-accumulate units with INT32 accumulation. On-chip feature and weight buffers hold tensors, a line buffer forms sliding windows for kernels up to 7 by 7, and an AXI4 256-bit DMA with a tile engine and double buffer streams data. A layer sequencer walks the model while activation, pooling and batchnorm stages close the pipeline.
| Category | AI accelerator, convolution engine |
|---|---|
| Compute | 16 by 16 systolic PE array, 256 INT8 MAC units |
| Precision | INT8 activations and weights, INT32 accumulator and bias, INT8 quantized output |
| Convolution | Kernels up to 7 by 7, stride up to 4, padding up to 3, up to 1024 input and output channels |
| Feature memory | On-chip feature buffer, 4096 deep, double buffered, 128-bit word |
| Weight memory | On-chip weight buffer, 4096 deep, 4 banks, with active and shadow prefetch |
| Sliding window | Line buffer for images up to 1024 pixels wide |
| Dataflow | Weight-stationary, output-stationary and row-stationary modes |
| Layer operations | Conv2D, depthwise, pointwise, pooling, upsample, concat, residual add, batchnorm, detection head |
| Post-processing | Activation LUT 256 deep (ReLU, ReLU6, SiLU, sigmoid, tanh, leaky), pooling (max, avg, global) |
| Host interface | APB CSR (4K register space, 32-bit registers), AXI-Stream feature, weight and result ports |
| Memory interface | AXI4 256-bit master DMA (32-bit address), tile engine, double buffer, SRAM macro port |
| Telemetry | Layer sequencer, 8 performance counters (48-bit), PE and bandwidth utilization |
| Verification | UVM VIP, golden-model scoreboard, functional coverage |
| Ownership | WIOWIZ IP and WIOWIZ VIP |
A 16 by 16 systolic PE array with INT32 accumulation for dense convolution.
Double-buffered feature memory and a 4-bank weight buffer keep tensors on-die.
A 256-bit master DMA with a tile engine and double buffer streams data to and from DDR.
Weight, output and row stationary modes adapt to layer shape and reuse.
Activation LUT, pooling, batchnorm and skip paths run inline after compute.
Golden-model scoreboard and coverage, WIOWIZ IP and VIP.
