One native flow from RTL to GDSII, implementation, verification and sign-off, each stage a WIOWIZ engine with AI and evidence built in. See the flow on the How It Works page.
WIOWIZ-native engines available today, in active use across our own silicon flow.
Native RTL-to-place-and-route implementation engine, synthesis through routing.
FSimXSIMRTL and gate-level logic simulation for SoC and chip.
vWIZ-WaveDEBUGWaveform viewer and interactive debug.
vWIZ-CoverageCOVCode, functional, assertion and formal coverage closure.
Hetu-FormalFVFormal property and equivalence verification.
TrutiCDCCDC and RDC structural audit and sign-off.
vWIZ-LintRTL LINTStandalone RTL lint with a no-false-clean guarantee.
Vajra-LPPOWERLow-power and UPF power-intent verification.
WZSpiceSPICETransistor-level and mixed-signal simulation.
Backend and sign-off engines on our roadmap toward autonomizing the RTL-to-GDSII flow — in active R&D, not yet released.
Tools under research stage →