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Truti

CDC and RDC structural audit and sign-off  ·  part of the WIOWIZ verification flow

Every asynchronous crossing, structurally accounted for

Truti is WIOWIZ's clock-domain crossing and reset-domain crossing analysis tool. It elaborates the RTL structure, establishes the design's real clocks, resets and domain constraints, then builds the crossing graph and applies CDC and RDC rules to find signals that move between asynchronous domains without safe synchronization. Every finding carries severity, source and destination paths, file and line evidence, and a rule-specific repair hint, and a run resolves to an explicit structural verdict rather than an unexplained pass.

CDCRDCSynchronizersReconvergenceDomain matrixSetup auditSign-off

What it checks

Clock-domain crossings

Detects single-bit data and control crossings and multi-bit transfers between asynchronous clock domains, built on a modelled map of clocks, generated clocks and port domains.

Synchronizer checks

Recognizes two-flop and multi-stage synchronizer chains, Gray-coded and FIFO-related structures, and quasi-static controls, then flags data crossings that lack a safe structure.

Reset-domain crossings

Analyses reset synchronizers, reset release and asynchronous reset assertion and deassertion, covering interactions across the design's reset tree.

Glitch and reconvergence

Reports asynchronous-control and mux-control paths, multi-bit coherency hazards, and reconvergence and convergence-clock integrity where crossings recombine downstream.

Structural sign-off

Resolves the analyzed scope to CLEAN, REVIEW, DIRTY or SETUP_BLOCKED, with a setup-coverage audit, waiver provenance and reviewer-bound disposition so an approval is tied to its evidence.

RTL structural analysis

Works from elaborated RTL hierarchy through the native FSimX handoff, with deterministic finding fingerprints and hierarchical block models for a block-then-top methodology.

Support

Stage RTL integrity, CDC and RDC structural audit and sign-off triage
Analysis Clock-domain and reset-domain crossings, synchronizer recognition, reconvergence and convergence integrity, multi-bit coherency
Inputs Synthesizable Verilog and SystemVerilog RTL with clock, reset and domain constraints
Outputs JSON, HTML and SARIF reports, domain matrix and crossing schematic, setup and waiver audits, structural verdict
Design level RTL structural, technology independent (no PDK required)
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