// ANALOG IP

Analog, mixed-signal and PHY IP, across foundry PDKs

RF, beamforming, compute-in-memory and sensor IP qualified on multiple PDKs, plus a Universal PHY of reusable building blocks and a protocol-configurable Unified PHY.

        Note: WIOWIZ analog IP is not silicon-proven and not
        compliance-certified. It is delivered as behavioral models with control
        RTL, functionally verified in simulation.
      

PDK availability

Analog and physical IP delivered as behavioral models with control RTL, qualified on the process technologies below.

IP	Function	Process node	Foundry / PDK	Maturity
RF Frontend	BLE and radar transceiver	130nm SiGe BiCMOS	IHP SG13G2	Silicon-calibrated model
Beamforming / Phased Array	mmWave weighting and steering	130nm SiGe BiCMOS	IHP SG13G2	Model + RTL
CAN PHY	Automotive line driver	180nm	GF180	Model + RTL
Compute-in-Memory	CIM macro and flash ADC	130nm	SkyWater Sky130	Model + RTL
PVT Sensor	Process, voltage, temperature	130nm	Sky130 / GF130	Digital RTL + model
Universal PHY (analog)	SerDes front-end primitives	130nm and advanced	IHP SG13G2, Sky130, GF130	Behavioral + RTL

Additional process ports are available on request. Maturity reflects proof-on-disk status, not standards certification.

Universal PHY (UPHY)

A library of shared physical-interface building blocks, the encoding, clocking and I/O primitives that many protocols reuse.

Encoding

8b/10b, 64b/66b

→

Scrambler / PRBS

data conditioning

→

Elastic FIFO

clock crossing

→

TX Driver

serializer

→

RX / CDR

deserialize, recover

→

I/O Pads

channel model

shared clocking and PLL primitives underpin the chain

Reused across eDP, MIPI, PCIe, UCIe, memory and SoC PHY interfaces.

Unified PHY

A single, protocol-configurable SerDes PHY. One physical layer serves many protocols by reconfiguring its logical and analog stages, distinct from the UPHY building-block library.

Protocol Layer

PCIe, USB, UCIe, CXL

→

PCS

encode, align, scramble

→

PMA / SerDes

TX, RX, CDR, equal.

→

Lane Manager

multi-lane, config

→

AFE / Pads

analog front-end

reference clock and per-lane PLL, software-selectable rate and protocol

One PHY instance, many standards, configured at integration time.