Vajra-LP reads IEEE 1801 (UPF) power intent, and, optionally, a gate netlist and Liberty, and checks that the structure of your power architecture is right without simulating a single vector. It is a static low-power verifier and debugger that catches power-intent mistakes early, so power domains, isolation, level shifters, retention and power switches are consistent before power-aware simulation begins.
Reads IEEE 1801 (UPF) power intent and builds the supply-net and power-state view the checks run against.
Verifies isolation and level-shifter structure on signals that cross between power domains, without simulation.
Checks that retention strategy on state elements is structurally consistent with the power intent.
Examines power-switch structure and the power-gating architecture described in the UPF.
Validates power-domain definitions and their supply-net associations across the design.
Optionally correlates the power intent against a gate netlist and Liberty for structure-level checks.
| Stage | Static low-power verification, UPF power-intent debug |
|---|---|
| Method | Structural checks of the power architecture, without simulation |
| Checks | Power domains, isolation, level shifters, retention, power switches, supply nets |
| Inputs | IEEE 1801 (UPF) power intent; optional gate netlist and Liberty |
| Outputs | Classified findings and static power-aware evidence for correlation downstream |
| Design level | RTL and gate, UPF-driven, technology independent (Liberty optional, no PDK required) |
