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Asesha

Signoff-Driven Coverage & Verification Metrics  ·  part of the WIOWIZ verification flow
PRODUCT UPDATE · AUGUST 2026

Asesha is now signoff-driven. It grades PASS with SILVER or GOLD from the closure that exists, adds power-aware closure with a dedicated DVFS board, and marks Covergroups and Formal as N/A rather than zero when a design has none. The tool, repository and commands remain vwiz-cov.

Every coverage type, one closure picture

Asesha brings code, functional, assertion, formal and power-aware coverage into a single closure picture, merges across a full regression, and grades the result it can defend. It marks a family it did not measure as N/A rather than zero, and shows Raw, Adjusted and UNR side by side, so a scope pushed green by exclusions cannot hide.

Asesha closure cockpit, verdict PASS grade SILVER
Asesha on the safety-MCU example, verdict PASS, grade SILVER
ClosureCodeToggleFSMAssertionsFunctionalFormal · UNRPowerDVFSRetentionEvidence

What it covers

Code coverage

Line, toggle, FSM, branch and expression under one parent, with source drill-down.

Functional coverage

Covergroups, bins and crosses. A design with none reads N/A, not a false zero.

Assertions

SVA assertion status, kept separate from code coverage, not folded in.

Formal · UNR

Unreachable and observability fold in, and read NOT COLLECTED until a proof bundle is imported.

Power-aware closure

Domains, isolation, retention, wake and DVFS from UPF intent, kept as a separate model.

Grade and ledger

A defensible grade, PASS with SILVER or GOLD, and an append-only audit ledger for every denominator change.

Power measured as itself

Power-aware coverage is a separate model, never averaged into the code number. DVFS is reported as four separate measurements: operating points, legal transitions, forbidden transitions and negative controls. A forbidden transition that never fires is desired behaviour, so it never shares a denominator with the legal edges.

Asesha DVFS board: operating points 3/3, legal 4/4, forbidden 2 declared 0 completed, negative controls 2 attempted and rejected
The DVFS board: voltage and frequency read from the UPF, forbidden edges protected by negative controls

Support

Stage Verification, coverage closure
Coverage types Code (line, toggle, FSM, branch, expression), functional (covergroups, bins, cross), assertion, formal UNR, power-aware (UPF)
Inputs Coverage databases from FSimX simulation and Hetu-Formal
Outputs Merged coverage reports, ranked holes, closure dashboard
Design level RTL and gate, technology independent (no PDK required)
Flow Native stage in the WIOWIZ CLI, with an append-only audit ledger
Grades PASS with SILVER or GOLD, from the strength of the closure that exists
Commands vwiz-cov, vwiz-cov-view (repository and namespace unchanged)

See it run

Asesha walkthrough

The closure boards, from cockpit to ledger, on the live GUI.

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