// EDA · RESEARCH & DEVELOPMENT
The road to full-flow sign-off
Our beta-stage tools already cover simulation, debug, coverage,
formal, CDC, power and SPICE. These backend and sign-off engines
complete the WIOWIZ RTL-to-GDSII vision. They are in research and
development — described here for what they will do, not offered
as released products.
← back to beta-stage EDA tools
LECR&D
Logic Equivalence Check
Proves two representations of a design are logically identical, so
transformations along the flow are provably safe.
-
RTL vs. synthesized netlist, and netlist vs. netlist after DFT
insertion, ECOs and place-and-route
-
Combinational and sequential equivalence with key-point matching
- Non-equivalence debug down to the failing cone of logic
STAR&D
Static Timing Analysis · pre / post-layout
Vectorless timing sign-off across the operating space, from early
estimates to final extracted timing.
-
Setup and hold across process, voltage and temperature corners
- On-chip variation and multi-mode multi-corner analysis
-
Pre-layout on estimated parasitics, post-layout on extracted RC
for closure
DFTR&D
Design-for-Test · scan · ATPG · MBIST
Testability built into the netlist so manufactured silicon can be
screened for defects.
- Scan-chain insertion and reordering
- ATPG for stuck-at and at-speed (transition) faults
- Memory BIST (MBIST) and boundary scan (JTAG)
Sign-offR&D
Physical sign-off · GDSII · DRC · LVS · PEX
Manufacturing sign-off of the final layout, feeding accurate
parasitics back into timing and power closure.
- DEF-to-GDSII streaming and layout generation (vWIZ-GDS)
- Design-rule checking (DRC) against the foundry deck
- Layout-versus-schematic (LVS) connectivity match
-
Parasitic extraction (PEX) of RC for accurate back-annotation
Where this sits. WIOWIZ is on a mission to autonomize the
RTL-to-GDSII flow. Simulation, debug and coverage are in beta today; this
back-end layer is the long-term roadmap toward place-and-route and GDSII
sign-off, in active R&D.
