WIOWIZ AI wiowiz AI
// FSimX · SIMULATION

RTL and gate-level simulation, WIOWIZ-native

SystemVerilog, UVM and RISC-V co-simulation on our own front-end — built to hold up at gate-level and UVM scale.

// vWIZ-Wave · DEBUG

Waveform debug that stays live at SoC scale

Subscribe-only tracing, cross-probe to source, and a transaction analyzer that decodes bus traffic straight off the wave.

// vWIZ-Coverage · CLOSURE

One coverage picture, code to formal

Code, functional and assertion coverage merged with formal UNR — finish with evidence, not assumptions.

// FSimX STUDIO · DOWNLOAD

Simulation, debug and coverage in one window

The FSimX engine, vWIZ-Wave and vWIZ-Coverage in one persistent session. Linux and Windows.

WIOWIZ AIobserve, learn, repeat and evolve with consciousness memory
01
RTL & Sim
FSimX
Hetu-Formal
02
Implement
APARA
RTL to PnR
03
Timing
static timing
in research
04
Power & DFT
Vajra-LP
DFT · in research
05
Signoff
DRC / LVS / PEX
in research
06
GDSII
tape-out ready
the traditional flow, augmented with AI at every stage
// FRONT-END SUITE · BETA

An EDA stack we build ourselves BETA

APARA RTL→PnR

Native RTL-to-place-and-route implementation engine.

FSimX SIM

RTL and gate-level logic simulation.

vWIZ-Wave DEBUG

Waveform viewer and interactive debug.

vWIZ-Coverage COV

Code, functional, assertion and formal coverage closure.

Hetu-Formal FV

Formal property and equivalence verification.

Truti CDC

CDC and RDC structural audit and sign-off.

vWIZ-Lint RTL LINT

Standalone RTL lint with a no-false-clean guarantee.

Vajra-LP POWER

Low-power and UPF power-intent verification.

WZSpice SPICE

Transistor-level and mixed-signal simulation.

Backend sign-off tools (LEC, STA, DFT, physical) are in research →
// SOFT IP & VIP

An indigenous IP portfolio, on our own RISC-V