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SOFT IP / AI ACCELERATORS / GPU

GPU — Graphics and Compute Processor

Programmable 16-SM shader and compute pipeline  ·  WIOWIZ IP and WIOWIZ VIP

16 streaming multiprocessors on a shared crossbar fabric

A programmable GPU built from 16 streaming multiprocessors, each running 32-thread warps on a 32-lane FP32 fused multiply-add datapath backed by a 256-register-per-thread file and 64 KB of banked shared memory. A command processor and work distributor dispatch thread blocks, a Greedy-Then-Oldest scheduler issues one warp per cycle, and memory traffic is coalesced onto a WAI crossbar into a 4 MB banked L2 with stride prefetch and a DRAM scheduler.

Host Register Interface, Command Processor and Work Distributor FRONT-END SHADER CORES MEMORY Command Processor register command model Work Distributor thread blocks to SMs Warp Scheduler 8 warps, GTO 16x Streaming Multiprocessor 32-thread warps 32-lane FP32 FMA 256 regs per thread 64 KB shared memory Coalescer / LDST 32 lanes per warp L2 Cache 4 banks, 4 MB, 8-way DRAM Scheduler stride prefetch WAI Crossbar Fabric (18 initiators, 6 targets) to L2 banks and DRAM
Clean architectural view. Real parameters from the WIOWIZ GPU RTL.

Specifications

Category Programmable GPU, graphics and compute pipeline
Shader cores 16 streaming multiprocessors (SMs)
Threading 32 threads per warp, 8 warp slots per SM
Compute 32-lane FP32 fused multiply-add per SM, 512 FP32 lanes across the GPU, 4-stage FMA pipeline
Integer Per-lane integer ALU (add, multiply, logic, shift, compare)
Register file 256 registers per thread
Shared memory 64 KB per SM, 32 banks
Warp scheduler Greedy-Then-Oldest, zero-cycle warp switch, one issue per cycle
L2 cache 4 banks, 4 MB total, 8-way, 64-byte lines, per-bank MSHR
Memory system WAI crossbar fabric, address coalescing, stride prefetch, DRAM scheduler with 4 request queues
ISA 64-bit fixed instructions, 32 KB shared instruction memory
Host interface Register and command interface, APB performance counters, WAI to AXI4 and APB4 bridges
Software stack Mesa Gallium driver, LLVM backend, reference assembler and ISA simulator
Verification UVM VIP, golden reference model, scoreboard and functional coverage
Ownership WIOWIZ IP and WIOWIZ VIP

Key features

16 SM shader array

Sixteen streaming multiprocessors run 32-thread warps on 32-lane FP32 FMA and per-lane integer ALUs.

GTO warp scheduling

A Greedy-Then-Oldest scheduler switches warps with zero cycle penalty and issues one warp every cycle.

64 KB shared memory

Each SM has 64 KB of 32-bank shared memory alongside a 256-register-per-thread file.

Coalesced memory access

Per-warp coalescing groups 32 lane addresses by cache line before issuing WAI requests.

4 MB banked L2

A four-bank, eight-way L2 with stride prefetch and a DRAM scheduler feeds the shader array.

Open software stack

A Mesa Gallium driver, LLVM backend, assembler and ISA simulator target the 64-bit ISA.

Applications

Embedded graphicsGPGPU computeCompute shadersEdge renderingSoC graphics subsystem
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