WIOWIZ AI wiowiz AI
SOFT IP / HIGH-SPEED INTERFACES / HBM

HBM Controller

High Bandwidth Memory controller and PHY interface  ·  WIOWIZ IP and WIOWIZ VIP

A JEDEC HBM controller from host port to PHY

A High Bandwidth Memory controller and PHY-facing interface covering HBM2, HBM2E and HBM3, with HBM3E and an HBM4 draft path. Per-channel controllers decompose the host address into channel, pseudo-channel, bank group, bank, row and column, an FR-FCFS scheduler tracks per-bank state and bank-group timing, and a DFI 5.0 interface drives the PHY, with on-die ECC, refresh management and PHY training built in.

AXI4 Host Port and APB CSR Configuration HOST & MAPPING SCHEDULING RAS & PHY AXI4 Host Port 256-bit data, 34-bit addr Address Mapper RBC, BRC, interleave Command Queue QoS and age based Command Scheduler FR-FCFS, row-hit first per-bank state FSMs tCCD and tFAW aware round-robin channels ECC and DBI SECDED, parity Refresh and RFM per-bank, adaptive DFI 5.0 Interface PHY training DFI 5.0 to HBM PHY (per channel, per pseudo-channel)
Clean architectural view. Real parameters from the WIOWIZ HBM RTL.

Specifications

Category Memory controller, High Bandwidth Memory interface
Standards JEDEC HBM2, HBM2E, HBM3 (HBM3E and HBM4 draft paths)
Interface width 1024-bit stack, 8 channels (HBM2) or 16 channels (HBM3), two pseudo-channels per channel
Bank topology Bank groups of four banks, up to 32 banks per channel (HBM3), CAS timing tracked per bank group
Access granularity 32-byte aligned access across all generations
Host interface AXI4 256-bit data, 34-bit address, APB CSR configuration
Scheduler FR-FCFS, row-hit priority, QoS and age based, tCCD and tFAW aware
Address mapping RBC, BRC, BRCC and RBCC schemes, channel and bank-group interleave
PHY interface DFI 5.0, configurable frequency ratio, integrated PHY training FSM
RAS On-die ECC (SECDED), data bus inversion, command and data parity, refresh management (RFM)
Refresh and power All-bank and per-bank refresh, temperature-adaptive rate, power-down, self-refresh, deep power-down
Verification UVM VIP, JEDEC timing SVA, scoreboard, functional coverage, DRAM model
Ownership WIOWIZ IP and WIOWIZ VIP

Key features

Multi-channel controller

Independent per-channel controllers with a round-robin arbiter on the shared host return path.

FR-FCFS scheduler

Row-hit first scheduling with per-bank state machines, bank-group timing and age-based anti-starvation.

Flexible address mapping

RBC, BRC and interleaved schemes trade open-page locality against multi-channel bandwidth.

DFI 5.0 PHY interface

Configurable frequency ratio and a training FSM covering write leveling, read DQS and VREF.

RAS built in

On-die ECC, data bus inversion, command and data parity, and refresh management alerts.

UVM-verified

JEDEC timing assertions, scoreboard and coverage, WIOWIZ IP and VIP.

Applications

AI and HPC acceleratorsGPU memory subsystemDatacenter SoCNetwork processors2.5D and 3D stacked memory
Request IP details