WIOWIZ AI wiowiz AI
SOFT IP / HIGH-SPEED INTERFACES / PCIe

PCIe Controller

PCI Express controller with layered protocol stack  ·  WIOWIZ IP and WIOWIZ VIP

A full PCI Express stack, from AXI to the PIPE interface

A synthesizable PCI Express controller that implements the complete layered stack. The Transaction Layer builds and parses TLPs, the Data Link Layer handles ACK and NAK replay and credit based flow control, and the Physical Layer interface drives an LTSSM over PIPE. A scatter-gather DMA engine and address translation move data across AXI4, while a config space carries the Type 0 and Type 1 headers with MSI, MSI-X and power management.

AXI4 Master and Slave  ·  APB Register Interface HOST & DMA PROTOCOL LAYERS LINK SERVICES DMA Engine scatter-gather, rd and wr Address Translation ATU, inbound and outbound Config Space Type 0 and Type 1, MSI-X Layered Stack Transaction Layer TLP build and parse Data Link Layer DLLP, LCRC, replay Physical Layer PIPE, ordered sets Flow Control credit based, InitFC LTSSM link training Replay Buffer ACK, NAK recovery PIPE Interface and SerDes Lanes (Gen1 to Gen5, x1 to x16)
Clean architectural view. Real parameters from the WIOWIZ PCIe controller RTL.

Specifications

Category High-speed interface, PCI Express controller
Protocol layers Transaction Layer, Data Link Layer, Physical Layer interface
Generations Gen1 to Gen5 (2.5, 5.0, 8.0, 16.0 and 32.0 GT/s), configurable max speed
Link width x1 to x16, configurable lane count
Encoding 8b/10b (Gen1 and Gen2), 128b/130b with scrambler (Gen3 and above)
Device types Endpoint, Root Complex, Switch
Config space 4 KB space, Type 0 and Type 1 headers, MSI, MSI-X, Power Management, AER
DMA Scatter-gather DMA engine, read and write channels, linked-list and ring modes, per-descriptor interrupt
Address translation ATU with inbound and outbound regions, first-match priority, bypass mode
Data Link services LCRC-32, DLLP CRC-16, ACK and NAK replay buffer, credit based flow control
Physical Layer PIPE interface, LTSSM, training and ordered sets, scrambler
System interface AXI4 master and slave, APB register interface
Verification UVM VIP, Root Complex and Endpoint models, scoreboard, protocol checkers, functional coverage
Ownership WIOWIZ IP and WIOWIZ VIP

Key features

Layered protocol stack

Transaction, Data Link and Physical layers implemented as clean, decoupled blocks.

Gen1 to Gen5

Configurable maximum speed from 2.5 GT/s to 32 GT/s across x1 to x16 lanes.

Scatter-gather DMA

Independent read and write channels with linked-list and ring descriptors over AXI4.

Config space and interrupts

Type 0 and Type 1 headers with MSI, MSI-X, power management and AER.

Reliable data link

ACK and NAK replay, LCRC and DLLP CRC, and credit based flow control.

UVM-verified

Root Complex and Endpoint models, scoreboard and coverage, WIOWIZ IP and VIP.

Applications

SoC host interfaceStorage and NVMeAccelerator attachNetworking and switchingEmbedded root complex
Request IP details