SOCVP is WIOWIZ's executable model of its own Soft IP, packaged as bootable SoC solutions that run real RISC-V firmware you compile yourself. Evaluate WIOWIZ IP without waiting for an RTL drop. It models WIOWIZ silicon at the architecture level, it is not an RTL simulator.
See it run ↓ See the EDA platformEach solution boots real firmware against a modelled WIOWIZ SoC, RISC-V processors, an INT8 NPU, DMA, PCIe and CXL endpoints, a UEC NIC and DPU, and more.
A compact RISC-V microcontroller SoC, the fastest way to boot real firmware and watch it pass.
An edge-inference SoC with the INT8 NPU, driven by shipped firmware and a golden reference.
A multi-core RISC-V SoC for concurrency, coherence and system bring-up.
A data-processing SoC with networking and CXL data movement for datacenter evaluation.
Every design here boots on the WIOWIZ engine. The numbers below come from an executed boot, not a specification.
| Design | Profile | Retired | Bus txns | Verdict |
|---|---|---|---|---|
| AI Edge SoC | RV32IM · CNN+NPU | 16,966 | 25,353 | Booted |
| Multicore | RV32 + RV64GC + safety | 2,312 | 11,725 | Booted |
| Networking DPU | descriptor DMA · loopback | 5,421 | 9,999 | Booted |
| MCU / controller | CPU · timer · IRQ · UART | 1,008 | 2,129 | Booted |
Bring your own SoC RTL is gated in this release. See Quickstart for the import envelope.
The IP a design can carry, and the level each is modeled at. A block absent from a solution is not modeled by that solution. MODELED executable model, gate-backed. BEHAVIORAL a characterized path, not full RTL.
| Block | Level | ai-edge | multicore | dpu | mcu | Notes |
|---|---|---|---|---|---|---|
| Memory | MODELED | O | O | O | O | Firmware and data storage |
| Console (UART) | MODELED | O | O | O | O | Prints characters from firmware |
| Timer and software interrupts | MODELED | O | O | O | O | Core-local interrupts |
| Timer | MODELED | O | O | X | O | Counts and raises periodic interrupts |
| Register block (APB) | MODELED | O | O | X | O | Memory-mapped registers |
| NPU (MAC tile) | MODELED | O | O | X | X | INT8 matrix multiply |
| NPU (systolic) | MODELED | O | O | X | X | INT8 8x8 systolic matrix-vector |
| Interrupt controller | MODELED | O | O | X | O | Routes and prioritises interrupts |
| Serial transmitter | MODELED | O | O | X | X | Frames bytes onto a serial line |
| Watchdog | MODELED | O | O | X | X | Resets the system if firmware stops feeding it |
| PWM | MODELED | O | O | X | X | Generates a duty-cycled output |
| CNN accelerator | MODELED | O | O | X | X | INT8 2D convolution |
| Max-pooling accelerator | MODELED | O | O | X | X | INT8 max-pooling |
| Sum-pooling accelerator | MODELED | O | O | X | X | INT8 sum-pooling |
| Depthwise convolution | MODELED | O | O | X | X | INT8 per-channel convolution |
| 1D convolution | MODELED | O | O | X | X | INT8 1D convolution |
| Elementwise add | MODELED | O | O | X | X | INT8 operands, INT32 accumulate |
| DMA engine | MODELED | O | O | X | X | Copies memory without the CPU |
| PCIe endpoint | BEHAVIORAL | O | O | X | X | Link training to L0, config space, BAR sizing |
| GPU (SIMT) | MODELED | O | O | X | X | FP32/INT32 kernels + divergent SIMT |
| CXL memory expander | MODELED | O | O | X | X | Type-3 coherent window, device MESI |
| Networking DPU | MODELED | O | O | O | X | Descriptor DMA and loopback packet copy |
Protocol-level detail such as link training and state machines lives in the Protocol Wizards, not here.
Short walk-throughs of SOCVP booting and evaluating WIOWIZ silicon.
The compact RISC-V microcontroller SoC boots shipped firmware and reports a checked pass.
A multi-core RISC-V SoC brings up concurrently with coherent memory traffic.
The edge SoC runs inference on the INT8 NPU and compares it element for element against a golden reference.
The data-processing SoC drives the UEC NIC and DPU datapath end to end.
PCIe endpoint transactions move through the modelled SoC with a full transaction log.
CXL coherent memory access is exercised and checked against the expected result.
From the package to a booted system in a few commands.
| Command | What it does |
|---|---|
| socvp solutions | what you can run |
| socvp boot <soc> | boot firmware on a solution |
| socvp studio <soc> | open the SoC studio |
| socvp evidence <soc> | what is proven, and what is not |
| socvp compare | functional vs RTL: same firmware, both engines |
| socvp import <rtl> | bring your own RTL to qualification |
| socvp check | verify complete system readiness |
Every flag is single-hyphen. Run socvp <command> -help for a command's options.
A boot ends in a verdict, and the verdict can fail. That is the point.
| Verdict | Meaning |
|---|---|
| Booted | the firmware booted and an oracle or check passed |
| Divergent | the model and the reference disagreed at a specific point |
| Incomplete | a required input or field was missing, so the run was refused |
| Blocked | a precondition was not met, a license or a dependency |
| Model required | the asset needs a model that is not present |
| Toolchain unavailable | a needed toolchain was not found on the host |
Timing, power, clock-domain crossing and RTL equivalence are not modeled on the portable engine. These render as not measured, never a green they did not earn.
Each strong check ships with a control that is meant to fail. If the check can pass a case it should reject, the control catches it. Proof sits next to its negative, not alone.
Every evaluation runs firmware and checks the result. Where a golden reference exists, the run is compared element for element.
A boot that executes an illegal instruction fails. A success flag cannot override a real fault.
The shipped package checks its own integrity and refuses to run a tampered file.
Boots are byte-for-byte deterministic. Run it ten times, diff nothing.
We learn the shape of a mature virtual-platform product, not its breadth. We aim to win the first ten minutes.
| Area | A general virtual platform | socvp |
|---|---|---|
| Goal | simulate a machine, a virtual embedded lab | boot and prove a silicon or IP package |
| Strength | boards, peripherals, scripting, ecosystem | the WIOWIZ engine, RTL truth, an evidence receipt |
| User action | describe a machine, run scripts | select or upload, then boot, prove, export |
| Debug | monitor, GDB, traces | boot log, system blocks, verdict, model vs RTL compare |
| Co-simulation | connect to third-party HDL simulators | runs RTL on our own FSiMX engine, no third-party |
| Best claim | simulate complex embedded systems | boot virtual silicon and show proof that can fail |
Where socvp is against the shape of a mature virtual-platform product. A capability moves to DONE only when a gate or an executed run proves it.
Delivered as a Docker bundle, the same image runs on Linux natively or on Windows via WSL2 with Ubuntu. Download, extract, build, and run. You always get the latest release.
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